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1. general description the PCA9626 is an i 2 c-bus controlled 24-bit led driver optimized for voltage switch dimming and blinking 100 ma red/green/blue/amber (rgba) leds. each led output has its own 8-bit resolution (256 steps) ?xed frequency individual pwm controller that operates at 97 khz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the led to be set to a speci?c brightness value. an additional 8-bit resolution (256 steps) group pwm controller has both a ?xed frequency of 190 hz and an adjustable frequency between 24 hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 % to 99.6 % that is used to either dim or blink all leds with the same value. each led output can be off, on (no pwm control), set at its individual pwm controller value or at both individual and group pwm controller values. the PCA9626 operates with a supply voltage range of 2.3 v to 5.5 v and the 100 ma open-drain outputs allow voltages up to 40 v. the PCA9626 is one of the ?rst led controller devices in a new fast-mode plus (fm+) family. fm+ devices offer higher frequency (up to 1 mhz) and more densely populated bus operation (up to 4000 pf). the active low output enable input pin ( oe) blinks all the led outputs and can be used to externally pwm the outputs, which is useful when multiple devices need to be dimmed or blinked together without using software control. software programmable led group and three sub call i 2 c-bus addresses allow all or de?ned groups of PCA9626 devices to respond to a common i 2 c-bus address, allowing for example, all red leds to be turned on or off at the same time or marquee chasing effect, thus minimizing i 2 c-bus commands. seven hardware address pins allow up to 126 devices on the same bus. the software reset (swrst) call allows the master to perform a reset of the PCA9626 through the i 2 c-bus, identical to the power-on reset (por) that initializes the registers to their default state causing the output nand fets to be off (led off). this allows an easy and quick way to recon?gure all device registers to the same condition. in addition to these features found in pca9633, pca9634, pca9635, pca9622 and pca9624, a new feature to control led output pattern is incorporated in the PCA9626. a new control byte called chase byte allows enabling or disabling of selective led outputs depending on the value of the chase byte. this feature greatly reduces the number of bytes to be sent to the PCA9626 when repetitive patterns need to be displayed as in creating a marquee chasing effect. if the PCA9626 on-chip 100 ma nand fets do not provide enough current or voltage to drive the leds, then the pca9635 and the pca9635 with larger current or higher voltage external drivers can be used. PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver rev. 01 2 june 2009 product data sheet
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 2 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 2. features n 24 led drivers. each output programmable at: u off u on u programmable led brightness u programmable group dimming/blinking mixed with individual led brightness n 1 mhz fast-mode plus compatible i 2 c-bus interface with 30 ma high drive capability on sda output for driving high capacitive buses n 256-step (8-bit) linear programmable brightness per led output varying from fully off (default) to maximum brightness using a 97 khz pwm signal n 256-step group brightness control allows general dimming (using a 190 hz pwm signal) from fully off to maximum brightness (default) n 256-step group blinking with frequency programmable from 24 hz to 10.73 s and duty cycle from 0 % to 99.6 % n 24 open-drain outputs can sink between 0 ma to 100 ma and are tolerant to a maximum off state voltage of 40 v. no input function. n output state change programmable on the acknowledge or the stop command to update outputs byte-by-byte or all at the same time (default to change on stop). n active low output enable ( oe) input pin allows for hardware blinking and dimming of the leds n 7 hardware address pins allow 126 PCA9626 devices to be connected to the same i 2 c-bus and to be individually programmed n 4 software programmable i 2 c-bus addresses (one led group call address and three led sub call addresses) allow groups of devices to be addressed at the same time in any combination (for example, one register used for all call so that all the PCA9626s on the i 2 c-bus can be addressed at the same time and the second register used for three different addresses so that 1 3 of all devices on the bus can be addressed at the same time in a group). software enable and disable for i 2 c-bus address. n a chase byte allows execution of prede?ned on/off pattern for the 24 led outputs n software reset feature (swrst call) allows the device to be reset through the i 2 c-bus n 25 mhz internal oscillator requires no external components n internal power-on reset n noise ?lter on sda/scl inputs n no glitch on power-up n supports hot insertion n low standby current n operating power supply voltage (v dd ) range of 2.3 v to 5.5 v n 5.5 v tolerant inputs on non-led pins n - 40 c to +85 c operation n esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 n latch-up testing is done to jedec standard jesd78 which exceeds 100 ma n packages offered: lqfp48, hvqfn48
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 3 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 3. applications n rgb or rgba led drivers n led status information n led displays n lcd backlights n keypad backlights for cellular phones or handheld devices 4. ordering information table 1. ordering information type number topside mark package name description version PCA9626b PCA9626 lqfp48 plastic low pro?le quad ?at package; 48 leads; body 7 7 1.4 mm sot313-2 PCA9626bs PCA9626 hvqfn48 plastic thermal enhanced very thin quad ?at package; no leads; 48 terminals; body 6 6 0.85 mm sot778-4
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 4 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 5. block diagram remark: only one led output shown for clarity. fig 1. block diagram of PCA9626 a0 a1 a2 a3 a4 a5 a6 002aad608 i 2 c-bus control input filter PCA9626 power-on reset scl sda v dd v ss led s tat e select register pwm register x brightness control grpfreq register grppwm register mux/ control oe '0' C permanently off '1' C permanently on ledn 190 hz 24.3 khz 97 khz 25 mhz oscillator fet driver
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 5 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 6. pinning information 6.1 pinning fig 2. pin con?guration for lqfp48 fig 3. pin con?guration for hvqfn48 a2 a3 a4 v ss led8 led9 led10 led11 v ss a5 a6 oe v ss led12 led13 led14 led15 v ss v ss led16 led17 led18 led19 v ss led7 v ss led6 led5 led4 v ss v ss led3 led2 led1 led0 v ss v ss a1 a0 v ss led23 led22 led21 led20 v dd sda scl v ss PCA9626b 002aad662 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24 002aad609 PCA9626bs v ss led7 v ss led12 led6 led13 led5 led14 led4 led15 v ss v ss v ss v ss led3 led16 led2 led17 led1 led18 led0 led19 v ss v ss a2 a3 a4 v ss led8 led9 led10 led11 v ss a5 a6 oe v ss a1 a0 v ss led23 led22 led21 led20 v dd sda scl v ss 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 6 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 6.2 pin description table 2. pin description symbol pin type description led22 43 o led driver 22 led23 44 o led driver 23 v ss 1, 6, 7, 12, 16, 21, 25, 30, 31, 36, 37, 45, 48 [1] power supply supply ground a0 46 i address input 0 a1 47 i address input 1 led0 2 o led driver 0 led1 3 o led driver 1 led2 4 o led driver 2 led3 5 o led driver 3 led4 8 o led driver 4 led5 9 o led driver 5 led6 10 o led driver 6 led7 11 o led driver 7 a2 13 i address input 2 a3 14 i address input 3 a4 15 i address input 4 led8 17 o led driver 8 led9 18 o led driver 9 led10 19 o led driver 10 led11 20 o led driver 11 a5 22 i address input 5 a6 23 i address input 6 oe 24 i active low output enable led12 26 o led driver 12 led13 27 o led driver 13 led14 28 o led driver 14 led15 29 o led driver 15 led16 32 o led driver 16 led17 33 o led driver 17 led18 34 o led driver 18 led19 35 o led driver 19 scl 38 i serial clock line sda 39 i/o serial data line v dd 40 power supply supply voltage led20 41 o led driver 20 led21 42 o led driver 21
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 7 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver [1] hvqfn48 package supply ground is connected to both v ss pins and exposed center pad. v ss pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. 7. functional description refer to figure 1 bloc k diag r am of PCA9626 . 7.1 device addresses following a start condition, the bus master must output the address of the slave it is accessing. there are a maximum of 128 possible programmable addresses using the 7 hardware address pins. two of these addresses, software reset and led all call, cannot be used because their default power-up state is on, leaving a maximum of 126 addresses. using other reserved addresses, as well as any other sub call address, will reduce the total number of possible addresses even further. 7.1.1 regular i 2 c-bus slave address the i 2 c-bus slave address of the PCA9626 is shown in figure 4 . to conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled high or low externally. remark: using reserved i 2 c-bus addresses will interfere with other devices, but only if the devices are on the bus and/or the bus will be open to other i 2 c-bus systems at some later date. in a closed system where the designer controls the address assignment these addresses can be used since the PCA9626 treats them like any other address. the led all call, software rest and pca9564 or pca9665 slave address (if on the bus) can never be used for individual device addresses. ? PCA9626 led all call address (1110 000) and software reset (0000 0110) which are active on start-up ? pca9564 (0000 000) or pca9665 (1110 000) slave address which is active on start-up ? reserved for future use i 2 c-bus addresses (0000 011, 1111 1xx) ? slave devices that use the 10-bit addressing scheme (1111 0xx) ? slave devices that are designed to respond to the general call address (0000 000) ? high-speed mode (hs-mode) master code (0000 1xx) fig 4. slave address r/w 002aab319 a6 a5 a4 a3 a2 a1 a0 hardware selectable slave address
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 8 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver the last bit of the address byte de?nes the operation to be performed. when set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 led all call i 2 c-bus address ? default power-up value (allcalladr register): e0h or 1110 000 ? programmable through i 2 c-bus (volatile programming) ? at power-up, led all call i 2 c-bus address is enabled. PCA9626 sends an ack when e0h (r/ w = 0) or e1h (r/ w = 1) is sent by the master. see section 7.3.9 allcalladr, led all call i 2 c-b us address for more detail. remark: the default led all call i 2 c-bus address (e0h or 1110 000) must not be used as a regular i 2 c-bus slave address since this address is enabled at power-up. all of the PCA9626s on the i 2 c-bus will acknowledge the address if sent by the i 2 c-bus master. 7.1.3 led sub call i 2 c-bus addresses ? 3 different i 2 c-bus addresses can be used ? default power-up values: C subadr1 register: e2h or 1110 001 C subadr2 register: e4h or 1110 010 C subadr3 register: e8h or 1110 100 ? programmable through i 2 c-bus (volatile programming) ? at power-up, sub call i 2 c-bus addresses are disabled. PCA9626 does not send an ack when e2h (r/ w = 0) or e3h (r/ w = 1), e4h (r/ w = 0) or e5h (r/ w = 1), or e8h (r/ w = 0) or e9h (r/ w = 1) is sent by the master. see section 7.3.8 subadr1 to subadr3, i 2 c-b us subaddress 1 to 3 for more detail. remark: the default led sub call i 2 c-bus addresses may be used as regular i 2 c-bus slave addresses as long as they are disabled. 7.1.4 software reset i 2 c-bus address the address shown in figure 5 is used when a reset of the PCA9626 needs to be performed by the master. the software reset address (swrst call) must be used with r/ w = logic 0. if r/ w = logic 1, the PCA9626 does not acknowledge the swrst. see section 7.6 softw are reset for more detail. remark: the software reset i 2 c-bus address is a reserved address and cannot be used as a regular i 2 c-bus slave address or as an led all call or led sub call address. fig 5. software reset address 0 002aab416 0 0 0 0 0 1 1 r/w
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 9 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.2 control register following the successful acknowledgement of the slave address, led all call address or led sub call address, the bus master will send a byte to the PCA9626, which will be stored in the control register. the lowest 6 bits are used as a pointer to determine which register will be accessed (d[5:0]). the highest bit is used as auto-increment flag (aif). this bit along with the mode1 register bit 5 and bit 6 provide the auto-increment feature. bit 6 of the control register is not used. when the auto-increment flag is set (aif = logic 1), the six low order bits of the control register are automatically incremented after a read or write. this allows the user to program the registers sequentially. four different types of auto-increment are possible, depending on ai1 and ai0 values of mode1 register. [1] ai1 and ai0 come from mode1 register. remark: other combinations not shown in t ab le 3 (aif + ai[1:0] = 001b, 010b, 011b and 111b) are reserved and must not be used for proper device operation. aif + ai[1:0] = 000b is used when the same register must be accessed several times during a single i 2 c-bus communication, for example, changes the brightness of a single led. data is overwritten each time the register is accessed during a write operation. aif + ai[1:0] = 100b is used when all the registers must be sequentially accessed, for example, power-up programming. reset state = 80h remark: the control register does not apply to the software reset i 2 c-bus address. fig 6. control register table 3. auto-increment options aif ai1 [1] ai0 [1] function 0 0 0 no auto-increment 1 0 0 auto-increment for all registers. d[5:0] roll over to 0h after the last register 26h is accessed. 1 0 1 auto-increment for individual brightness registers only. d[5:0] roll over to 2h after the last register (19h) is accessed. 1 1 0 auto-increment for global control registers and chase register. d[5:0] roll over to 1ah after the last register (1ch) is accessed. 1 1 1 auto-increment for individual brightness registers; global control registers and chase register. d[5:0] roll over to 2h after the last register (1ch) is accessed. 002aad610 aif x d5 d4 d3 d2 d1 d0 auto-increment flag register address don't care
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 10 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver aif + ai[1:0] = 101b is used when the 16 led drivers must be individually programmed with different values during the same i 2 c-bus communication, for example, changing color setting to another color setting. aif + ai[1:0] = 110b is used when the led drivers must be globally programmed with different settings during the same i 2 c-bus communication, for example, global brightness or blinking change. aif + ai[1:0] = 111b is used when the 16 led drivers must be individually programmed with different values in addition to global programming. only the 6 least signi?cant bits d[5:0] are affected by the aif, ai1 and ai0 bits. when the control register is written, the register entry point determined by d[5:0] is the ?rst register that will be addressed (read or write operation), and can be anywhere between 0h and 26h (as de?ned in t ab le 4 ). when aif = 1, the auto-increment flag is set and the rollover value at which the register increment stops and goes to the next one is determined by aif, ai1 and ai2. see t ab le 3 for rollover values. for example, if mode1 register bit ai1 = 0 and ai0 = 1 and if the control register = 1001 0010, then the register addressing sequence will be (in hex): 20 ? 21 ? ? 26 ? 0 ? 1 ? 2 ? ? 19 ? 02 ? 03 ? ? 19 ? 02 as long as the master keeps sending or reading data. 7.3 register de?nitions table 4. register summary [1] [2] register number (hex) d5 d4 d3 d2 d1 d0 name type function 00 000000 mode1 read/write mode register 1 01 000001 mode2 read/write mode register 2 02 000010 pwm0 read/write brightness control led0 03 000011 pwm1 read/write brightness control led1 04 000100 pwm2 read/write brightness control led2 05 000101 pwm3 read/write brightness control led3 06 000110 pwm4 read/write brightness control led4 07 000111 pwm5 read/write brightness control led5 08 001000 pwm6 read/write brightness control led6 09 001001 pwm7 read/write brightness control led7 0a 001010 pwm8 read/write brightness control led8 0b 001011 pwm9 read/write brightness control led9 0c 001100 pwm10 read/write brightness control led10 0d 001101 pwm11 read/write brightness control led11 0e 001110 pwm12 read/write brightness control led12 0f 001111 pwm13 read/write brightness control led13 10 010000 pwm14 read/write brightness control led14 11 010001 pwm15 read/write brightness control led15 12 010010 pwm16 read/write brightness control led16 13 010011 pwm17 read/write brightness control led17
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 11 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver [1] only d[5:0] = 00 0000 to 10 0110 are allowed and will be acknowledged. d[5:0] = 10 0111 to 11 1111 are reserved and may not be acknowledged. [2] when writing to the control register, bit 6 should be programmed with logic 0 for proper device operation. 14 010100 pwm18 read/write brightness control led18 15 010101 pwm19 read/write brightness control led19 16 010110 pwm20 read/write brightness control led20 17 010111 pwm21 read/write brightness control led21 18 011000 pwm22 read/write brightness control led22 19 011001 pwm23 read/write brightness control led23 1a 011010 grppwm read/write group duty cycle control 1b 011011 grpfreq read/write group frequency 1c 011100 chase read/write chase control 1d 011101 ledout0 read/write led output state 0 1e 011110 ledout1 read/write led output state 1 1f 011111 ledout2 read/write led output state 2 20 100000 ledout3 read/write led output state 3 21 100001 ledout4 read/write led output state 4 22 100010 ledout5 read/write led output state 5 23 100011 subadr1 read/write i 2 c-bus subaddress 1 24 100100 subadr2 read/write i 2 c-bus subaddress 2 25 100101 subadr3 read/write i 2 c-bus subaddress 3 26 100110 allcalladr read/write led all call i 2 c-bus address table 4. register summary [1] [2] continued register number (hex) d5 d4 d3 d2 d1 d0 name type function
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 12 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.1 mode register 1, mode1 [1] it takes 500 m s max. for the oscillator to be up and running once sleep bit has been set to logic 1. timings on ledn outputs are not guaranteed if pwmx, grppwm or grpfreq registers are accessed within the 500 m s window. [2] no blinking or dimming is possible when the oscillator is off. 7.3.2 mode register 2, mode2 [1] change of the outputs at the stop command allows synchronizing outputs of more than one PCA9626. applicable to registers fro m 02h (pwm0) to 08h (ledout) only. table 5. mode1 - mode register 1 (address 00h) bit description legend: * default value. bit symbol access value description 7 ai2 read only 0 register auto-increment disabled. 1* register auto-increment enabled. 6 ai1 r/w 0* auto-increment bi t 1 = 0. auto-increment range as de?ned in t ab le 3 . 1 auto-increment bi t 1 = 1. auto-increment range as de?ned in t ab le 3 . 5 ai0 r/w 0* auto-increment bi t 0 = 0. auto-increment range as de?ned in t ab le 3 . 1 auto-increment bi t 0 = 1. auto-increment range as de?ned in t ab le 3 . 4 sleep r/w 0 normal mode [1] . 1* low power mode. oscillator off [2] . 3 sub1 r/w 0* PCA9626 does not respond to i 2 c-bus subaddress 1. 1 PCA9626 responds to i 2 c-bus subaddress 1. 2 sub2 r/w 0* PCA9626 does not respond to i 2 c-bus subaddress 2. 1 PCA9626 responds to i 2 c-bus subaddress 2. 1 sub3 r/w 0* PCA9626 does not respond to i 2 c-bus subaddress 3. 1 PCA9626 responds to i 2 c-bus subaddress 3. 0 allcall r/w 0 PCA9626 does not respond to led all call i 2 c-bus address. 1* PCA9626 responds to led all call i 2 c-bus address. table 6. mode2 - mode register 2 (address 01h) bit description legend: * default value. bit symbol access value description 7 - read only 0* reserved 6 - read only 0* reserved 5 dmblnk r/w 0* group control = dimming. 1 group control = blinking. 4 invrt read only 0* reserved 3 och r/w 0* outputs change on stop command [1] 1 outputs change on ack 2 - read only 1* reserved 1 - read only 0* reserved 0 - read only 1* reserved
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 13 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.3 pwm0 to pwm23, individual brightness control a 97 khz ?xed frequency signal is used for each output. duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = led output at maximum brightness). applicable to led outputs programmed with ldrx = 10 or 11 (ledout0 to ledout5 registers). (1) table 7. pwm0 to pwm23 - pwm registers 0 to 23 (address 02h to 19h) bit description legend: * default value. address register bit symbol access value description 02h pwm0 7:0 idc0[7:0] r/w 0000 0000* pwm0 individual duty cycle 03h pwm1 7:0 idc1[7:0] r/w 0000 0000* pwm1 individual duty cycle 04h pwm2 7:0 idc2[7:0] r/w 0000 0000* pwm2 individual duty cycle 05h pwm3 7:0 idc3[7:0] r/w 0000 0000* pwm3 individual duty cycle 06h pwm4 7:0 idc4[7:0] r/w 0000 0000* pwm4 individual duty cycle 07h pwm5 7:0 idc5[7:0] r/w 0000 0000* pwm5 individual duty cycle 08h pwm6 7:0 idc6[7:0] r/w 0000 0000* pwm6 individual duty cycle 09h pwm7 7:0 idc7[7:0] r/w 0000 0000* pwm7 individual duty cycle 0ah pwm8 7:0 idc8[7:0] r/w 0000 0000* pwm8 individual duty cycle 0bh pwm9 7:0 idc9[7:0] r/w 0000 0000* pwm9 individual duty cycle 0ch pwm10 7:0 idc10[7:0] r/w 0000 0000* pwm10 individual duty cycle 0dh pwm11 7:0 idc11[7:0] r/w 0000 0000* pwm11 individual duty cycle 0eh pwm12 7:0 idc12[7:0] r/w 0000 0000* pwm12 individual duty cycle 0fh pwm13 7:0 idc13[7:0] r/w 0000 0000* pwm13 individual duty cycle 10h pwm14 7:0 idc14[7:0] r/w 0000 0000* pwm14 individual duty cycle 11h pwm15 7:0 idc15[7:0] r/w 0000 0000* pwm15 individual duty cycle 12h pwm16 7:0 idc16[7:0] r/w 0000 0000* pwm16 individual duty cycle 13h pwm17 7:0 idc17[7:0] r/w 0000 0000* pwm17 individual duty cycle 14h pwm18 7:0 idc18[7:0] r/w 0000 0000* pwm18 individual duty cycle 15h pwm19 7:0 idc19[7:0] r/w 0000 0000* pwm19 individual duty cycle 16h pwm20 7:0 idc20[7:0] r/w 0000 0000* pwm20 individual duty cycle 17h pwm21 7:0 idc21[7:0] r/w 0000 0000* pwm21 individual duty cycle 18h pwm22 7:0 idc22[7:0] r/w 0000 0000* pwm22 individual duty cycle 19h pwm23 7:0 idc23[7:0] r/w 0000 0000* pwm23 individual duty cycle duty cycle idcx 7 : 0 [] 256 --------------------------- =
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 14 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.4 grppwm, group duty cycle control when dmblnk bit (mode2 register) is programmed with logic 0, a 190 hz ?xed frequency signal is superimposed with the 97 khz individual brightness control signal. grppwm is then used as a global brightness control allowing the led outputs to be dimmed with the same value. the value in grpfreq is then a dont care. general brightness for the 16 outputs is controlled through 256 linear steps from 00h (0 % duty cycle = led output off) to ffh (99.6 % duty cycle = maximum brightness). applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout5 registers). when dmblnk bit is programmed with logic 1, grppwm and grpfreq registers de?ne a global blinking pattern, where grpfreq contains the blinking period (from 24 hz to 10.73 s) and grppwm the duty cycle (on/off ratio in %). (2) 7.3.5 grpfreq, group frequency grpfreq is used to program the global blinking period when dmblnk bit (mode2 register) is equal to 1. value in this register is a dont care when dmblnk = 0. applicable to led outputs programmed with ldrx = 11 (ledout0 to ledout5 registers). blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 hz) to ffh (10.73 s). (3) table 8. grppwm - group brightness control register (address 1ah) bit description legend: * default value address register bit symbol access value description 1ah grppwm 7:0 gdc[7:0] r/w 1111 1111 grppwm register duty cycle gdc 7 : 0 [] 256 -------------------------- - = table 9. grpfreq - group frequency register (address 1bh) bit description legend: * default value. address register bit symbol access value description 1bh grpfreq 7:0 gfrq[7:0] r/w 0000 0000* grpfreq register global blinking period gfrq 7 : 0 [] 1 + 24 --------------------------------------- - s () =
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 15 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.6 chase control chase is used to program the led output on/off pattern. the contents of the chase register is used to enable one of the led output patterns, as indicated in t ab le 11 . by repeated, sequential access to this table via the chase register, a chase pattern, e.g., marquee effect, can be easily programmed with minimal number of commands. once the chase register is accessed, the data bytes that follow will be used as an index value to pick the led output patterns de?ned by t ab le 11 chase sequence . this register always updates on ack. it is used to gate the oe signal at each of the ledn pins such that: ? oe = 1: all leds are off ? oe = 0: those leds corresponding to the xs in t ab le 11 are on any write to this register takes effect at the ack. table 10. chase - chase pattern control register (address 1ch) bit description legend: * default value. address register bit symbol access value description 1ch chase 7:0 chc[7:0] r/w 0000 0000* chase register
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 16 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver table 11. chase sequence x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 00 00xxxxxxxxxxxxxxxxxxxxxxxx all leds on 01 01 all leds off 02 02xxxxxxxxxxxx 1 2 chase a 03 03xxxxxxxxxxxx 1 2 chase b 0404xxxxxxxx 1 3 chase a 0505xxxxxxxx 1 3 chase b 0606xxxxxxxx 1 3 chase c 07 07 x ltr_0_on (1 left to right_start) 08 08 x ltr_1_on 09 09 x ltr_2_on 10 0a x ltr_3_on 11 0b x ltr_4_on 12 0c x ltr_5_on 13 0d x ltr_6_on 14 0e x ltr_7_on 15 0f x ltr_8_on 16 10 x ltr_9_on 17 11 x ltr_10_on 18 12 x ltr_11_on 19 13 x ltr_12_on 20 14 x ltr_13_on 21 15 x ltr_14_on 22 16 x ltr_15_on 23 17 x ltr_16_on 24 18 x ltr_17_on 25 19 x ltr_18_on 26 1a x ltr_19_on 27 1b x ltr_20_on
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 17 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 28 1c x ltr_21_on 29 1d x ltr_22_on 30 1e x ltr_23_on (1 left to right_end) 31 1f x x 2 left to right_start 32 20 x x 33 21 x x 34 22 x x 35 23 x x 36 24 x x 37 25 x x 38 26 x x 39 27 xx 40 28 xx 41 29 xx 42 2a xx2 left to right_end 43 2b x x x 3 left to right_start 44 2c x x x 45 2d x x x 46 2e x x x 47 2f x x x 48 30 xxx 49 31 xxx 50 32 xxx3 left to right_end 51 33 x x x x 4 left to right_start 52 34 x x x x 53 35 xxxx 54 36 xxxx 55 37 xxxx table 11. chase sequence continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 18 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 56 38 xxxx4 left to right_end 57 39xxxxx 5 left to right_start 58 3a xxxxx 59 3b xxxxx 60 3c xxxxx 61 3d xxxx5 left to right_end 62 3exxxxxx 6 left to right_start 63 3f xxxxxx 64 40 xxxxxx 65 41 xxxxxx6 left to right_end 66 42 x x1 implode_start 67 43 x x 68 44 x x 69 45 x x 70 46 x x 71 47 x x 72 48 x x 73 49 x x 74 4a x x 75 4b x x 76 4c x x 77 4d x x 1 implode_end 78 4e x x xx2 implode_start 79 4f x x xx 80 50 x x x x 81 51 x x x x 82 52 x x x x 83 53 x x x x 84 54 x x 2 implode_end table 11. chase sequence continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 19 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 85 55 x x x xxx3 implode_start 86 56 xxx xxx 87 57 x x x x x x 88 58 xxxxxx 89 59 x x x x 90 5a x x 3 implode_end 91 5b x x x x xxxx4 implode_start 92 5c xxxx xxxx 93 5d xxxxxxxx 94 5e x x x x 95 5f x x 4 implode_end 96 60 all led outputs disabled for chase byte = 60h to ffh. reserved for future use. table 11. chase sequence continued x = enabled; empty cell = disabled. command hex led channel description 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 20 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.7 ledout0 to ledout5, led driver output state ldrx = 00 led driver x is off (default power-up state). ldrx = 01 led driver x is fully on (individual brightness and group dimming/blinking not controlled). ldrx = 10 led driver x individual brightness can be controlled through its pwmx register. ldrx = 11 led driver x individual brightness and group dimming/blinking can be controlled through its pwmx register and the grppwm registers. table 12. ledout0 to ledout5 - led driver output state register (address 1dh to 22h) bit description legend: * default value. address register bit symbol access value description 1dh ledout0 7:6 ldr3 r/w 00* led3 output state control 5:4 ldr2 r/w 00* led2 output state control 3:2 ldr1 r/w 00* led1 output state control 1:0 ldr0 r/w 00* led0 output state control 1eh ledout1 7:6 ldr7 r/w 00* led7 output state control 5:4 ldr6 r/w 00* led6 output state control 3:2 ldr5 r/w 00* led5 output state control 1:0 ldr4 r/w 00* led4 output state control 1fh ledout2 7:6 ldr11 r/w 00* led11 output state control 5:4 ldr10 r/w 00* led10 output state control 3:2 ldr9 r/w 00* led9 output state control 1:0 ldr8 r/w 00* led8 output state control 20h ledout3 7:6 ldr15 r/w 00* led15 output state control 5:4 ldr14 r/w 00* led14 output state control 3:2 ldr13 r/w 00* led13 output state control 1:0 ldr12 r/w 00* led12 output state control 21h ledout4 7:6 ldr19 r/w 00* led19 output state control 5:4 ldr18 r/w 00* led18 output state control 3:2 ldr17 r/w 00* led17 output state control 1:0 ldr16 r/w 00* led16 output state control 22h ledout5 7:6 ldr23 r/w 00* led23 output state control 5:4 ldr22 r/w 00* led22 output state control 3:2 ldr21 r/w 00* led21 output state control 1:0 ldr20 r/w 00* led20 output state control
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 21 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.3.8 subadr1 to subadr3, i 2 c-bus subaddress 1 to 3 subaddresses are programmable through the i 2 c-bus. default power-up values are e2h, e4h, e8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding subx bit in mode1 register is equal to 0). once subaddresses have been programmed to their right values, subx bits need to be set to logic 1 in order to have the device acknowledging these addresses (mode1 register). only the 7 msbs representing the i 2 c-bus subaddress are valid. the lsb in subadrx register is a read-only bit (0). when subx is set to logic 1, the corresponding i 2 c-bus subaddress can be used during either an i 2 c-bus read or write sequence. 7.3.9 allcalladr, led all call i 2 c-bus address the led all call i 2 c-bus address allows all the PCA9626s on the bus to be programmed at the same time (allcall bit in register mode1 must be equal to logic 1 (power-up default state)). this address is programmable through the i 2 c-bus and can be used during either an i 2 c-bus read or write sequence. the register address can also be programmed as a sub call. only the 7 msbs representing the all call i 2 c-bus address are valid. the lsb in allcalladr register is a read-only bit (0). if allcall bit = 0, the device does not acknowledge the address programmed in register allcalladr. table 13. subadr1 to subadr3 - i 2 c-bus subaddress registers 0 to 3 (address 23h to 25h) bit description legend: * default value. address register bit symbol access value description 23h subadr1 7:1 a1[7:1] r/w 1110 001* i 2 c-bus subaddress 1 0 a1[0] r only 0* reserved 24h subadr2 7:1 a2[7:1] r/w 1110 010* i 2 c-bus subaddress 2 0 a2[0] r only 0* reserved 25h subadr3 7:1 a3[7:1] r/w 1110 100* i 2 c-bus subaddress 3 0 a3[0] r only 0* reserved table 14. allcalladr - led all call i 2 c-bus address register (address 26h) bit description legend: * default value. address register bit symbol access value description 26h allcalladr 7:1 ac[7:1] r/w 1110 000* allcall i 2 c-bus address register 0 ac[0] r only 0* reserved
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 22 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 7.4 active low output enable input the active low output enable ( oe) pin, allows to enable or disable all the led outputs at the same time. ? when a low level is applied to oe pin, all the led outputs are enabled as de?ned by the chase register. ? when a high level is applied to oe pin, all the led outputs are high-impedance. the oe pin can be used as a synchronization signal to switch on/off several PCA9626 devices at the same time. this requires an external clock reference that provides blinking period and the duty cycle. the oe pin can also be used as an external dimming control signal. the frequency of the external clock must be high enough not to be seen by the human eye, and the duty cycle value determines the brightness of the leds. remark: do not use oe as an external blinking control signal when internal global blinking is selected (dmblnk = 1, mode2 register) since it will result in an unde?ned blinking pattern. do not use oe as an external dimming control signal when internal global dimming is selected (dmblnk = 0, mode2 register) since it will result in an unde?ned dimming pattern. 7.5 power-on reset when power is applied to v dd , an internal power-on reset holds the PCA9626 in a reset condition until v dd has reached v por . at this point, the reset condition is released and the PCA9626 registers and i 2 c-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.6 software reset the software reset call (swrst call) allows all the devices in the i 2 c-bus to be reset to the power-up state value through a speci?c formatted i 2 c-bus command. to be performed correctly, it implies that the i 2 c-bus is functional and that there is no device hanging the bus. the swrst call function is de?ned as the following: 1. a start command is sent by the i 2 c-bus master. 2. the reserved swrst i 2 c-bus address 0000 011 with the r/ w bit set to 0 (write) is sent by the i 2 c-bus master. 3. the PCA9626 device(s) acknowledge(s) after seeing the swrst call address 0000 0110 (06h) only. if the r/ w bit is set to 1 (read), no acknowledge is returned to the i 2 c-bus master. 4. once the swrst call address has been sent and acknowledged, the master sends 2 bytes with 2 speci?c values (swrst data byte 1 and byte 2): a. byte 1 = a5h: the PCA9626 acknowledges this value only. if byte 1 is not equal to a5h, the PCA9626 does not acknowledge it. b. byte 2 = 5ah: the PCA9626 acknowledges this value only. if byte 2 is not equal to 5ah, then the PCA9626 does not acknowledge it.
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 23 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver if more than 2 bytes of data are sent, the PCA9626 does not acknowledge any more. 5. once the right 2 bytes (swrst data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a stop command to end the swrst call: the PCA9626 then resets to the default value (power-up value) and is ready to be addressed again within the speci?ed bus free time (t buf ). the i 2 c-bus master must interpret a non-acknowledge from the PCA9626 (at any time) as a swrst call abort. the PCA9626 does not initiate a reset of its registers. this happens only when the format of the swrst call sequence is not correct. 7.7 individual brightness control with group dimming/blinking a 97 khz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each led. on top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 led outputs): ? a lower 190 hz ?xed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control. ? a programmable frequency signal from 24 hz to 1 10.73 hz (8 bits, 256 steps) with programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking control. minimum pulse width for ledn brightness control is 40 ns. minimum pulse width for group dimming is 20.48 m s. when m = 1 (grppwm register value), the resulting ledn brightness control + group dimming signal will have 2 pulses of the led brightness control signal (pulse width = n 40 ns, with n de?ned in pwmx register). this resulting brightness + group dimming signal above shows a resulting control signal with m = 4 (8 pulses). fig 7. brightness + group dimming signals 123456789101112 507 508 509 510 511 512 1234567891011 brightness control signal (ledn) m 256 2 40 ns with m = (0 to 255) (grppwm register) n 40 ns with n = (0 to 255) (pwmx register) 256 40 ns = 10.24 m s (97.6 khz) 12345678 12345678 group dimming signal resulting brightness + group dimming signal 256 2 256 40 ns = 5.24 ms (190.7 hz) 002aab417
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 24 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 8 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is de?ned as the start condition (s). a low-to-high transition of the data line while the clock is high is de?ned as the stop condition (p) (see figure 9 ). 8.2 system con?guration a device generating a message is a transmitter; a device receiving is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see figure 10 ). fig 8. bit transfer mba607 data line stable; data valid change of data allowed sda scl fig 9. de?nition of start and stop conditions mba608 sda scl p stop condition s start condition
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 25 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 8.3 acknowledge the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. a master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 10. system con?guration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 11. acknowledgement on the i 2 c-bus 002aaa987 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 26 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 9. bus transactions (1) see t ab le 4 for register de?nition. fig 12. write to a speci?c register a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aad612 data for register d[5:0] (1) x d5 d4 d3 d2 d1 d0 x control register auto-increment flag a acknowledge from slave a acknowledge from slave p stop condition fig 13. write to all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aad613 mode1 register x 0 0 0 0 0 0 1 control register auto-increment on a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) mode1 register selection mode2 register a acknowledge from slave subadr3 register a acknowledge from slave allcalladr register a acknowledge from slave
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 27 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver this example assumes that aif + ai[1:0] = 101b. fig 14. multiple writes to individual brightness registers only using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aad614 pwm0 register data x 0 0 0 0 1 0 1 control register auto-increment on a acknowledge from slave a acknowledge from slave p stop condition (cont.) (cont.) pwm0 register selection pwm1 register data a acknowledge from slave pwm22 register data a acknowledge from slave pwm23 register data a acknowledge from slave pwm0 register data a acknowledge from slave register rollover pwm22 register data a acknowledge from slave pwm23 register data a acknowledge from slave
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 28 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver this example assumes that the mode1[5] = 0 and mode1[6] = 0. fig 15. read all registers using the auto-increment feature a5 a4 a3 a2 a1 a0 0 a s a6 slave address start condition r/w acknowledge from slave 002aad615 x 0 0 0 0 0 0 1 control register auto-increment on a acknowledge from slave (cont.) (cont.) mode1 register selection data from mode1 register a acknowledge from master sr restart condition a5 a4 a3 a2 a1 a0 1 a a6 slave address r/w acknowledge from slave data from mode2 register a acknowledge from master data from pwm0 a acknowledge from master data from allcalladr register a acknowledge from master data from mode1 register a acknowledge from master (cont.) (cont.) data from last read byte a not acknowledge from master p stop condition (1) in this example, several PCA9626s are used and the same sequence (a) (above) is sent to each of them. (2) allcall bit in mode1 register is previously set to 1 for this example. (3) och bit in mode2 register is previously set to 1 for this example. fig 16. led all call i 2 c-bus address programming and led all call sequence example a5 a4 a3 a2 a1 a0 0 a s a6 slave address (1) start condition r/w acknowledge from slave 002aad616 x 1 0 0 1 1 0 1 control register auto-increment on a acknowledge from slave allcalladr register selection 0 1 0 1 0 1 x 1 new led all call i 2 c address (2) p stop condition a acknowledge from slave 0 1 0 1 0 1 0 a s 1 led all call i 2 c address start condition r/w acknowledge from the 4 devices x x 0 1 0 0 0 x control register a acknowledge from the 4 devices ledout register selection 1 0 1 0 1 0 1 0 ledout register (led fully on) p stop condition a acknowledge from the 4 devices the 16 leds are on at the acknowledge (3) sequence (a) sequence (b)
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 29 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 10. application design-in information (1) oe requires pull-up resistor if control signal from the master is open-drain. i 2 c-bus address = 0010 101x. fig 17. typical application PCA9626 led0 led1 sda scl oe v dd = 2.5 v, 3.3 v or 5.0 v i 2 c-bus/smbus master sda scl 10 k w oe 10 k w led2 led3 a0 a1 a2 v dd a3 a4 a5 a6 v ss 10 k w (1) led8 led9 led10 led11 up to 40 v led light bar led12 led13 led14 led15 up to 40 v led light bar v ss up to 40 v led4 led5 led6 led7 up to 40 v led light bar up to 40 v led16 led17 led18 led19 led light bar led20 led21 led22 led23 up to 40 v led light bar 002aad607 up to 40 v
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 30 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 11. limiting values [1] each bit must be limited to a maximum of 100 ma and the total package limited to 2400 ma due to internal busing limits. table 15. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage - 0.5 +6.0 v v i/o voltage on an input/output pin v ss - 0.5 5.5 v v drv(led) led driver voltage v ss - 0.5 40 v i o(ledn) output current on pin ledn - 100 ma i ol(tot) total low-level output current led driver outputs; v ol = 0.5 v [1] 2400 - ma i ss ground supply current per v ss pin - 800 ma p tot total power dissipation t amb =25 c - 1.8 w t amb =85 c - 0.72 w p/ch power dissipation per channel t amb =25 c - 100 mw t amb =85 c - 45 mw t stg storage temperature - 65 +150 c t amb ambient temperature operating - 40 +85 c
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 31 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 12. static characteristics [1] v dd must be lowered to 0.2 v in order to reset part. [2] each bit must be limited to a maximum of 100 ma and the total package limited to 2400 ma due to internal busing limits. table 16. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = - 40 cto+85 c; unless otherwise speci?ed. symbol parameter conditions min typ max unit supply v dd supply voltage 2.3 - 5.5 v i dd supply current on pin v dd ; operating mode; no load; f scl = 1 mhz v dd = 2.7 v - 0.5 4 ma v dd = 3.6 v - 1.5 6 ma v dd = 5.5 v - 13 18 ma i stb standby current on pin v dd ; no load; f scl = 0 hz; i/o = inputs; v i =v dd v dd = 2.7 v - 0.5 5 m a v dd = 3.6 v - 1.0 10 m a v dd = 5.5 v - 6 15 m a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.70 2.0 v input scl; input/output sda v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i ol low-level output current v ol = 0.4 v; v dd = 2.3 v 20 - - ma v ol = 0.4 v; v dd = 5.0 v 30 - - ma i l leakage current v i =v dd or v ss - 1- +1 m a c i input capacitance v i =v ss - 6 10 pf led driver outputs v drv(led) led driver voltage 0 - 40 v i ol low-level output current v ol = 0.5 v; v dd 3 4.5 v [2] 100 - - ma r on on-state resistance v drv(led) = 40 v; v dd = 2.3 v - 2 5 w c o output capacitance - 15 40 pf oe input v il low-level input voltage - 0.5 - +0.8 v v ih high-level input voltage 0.7v dd - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf address inputs v il low-level input voltage - 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd - 5.5 v i li input leakage current - 1- +1 m a c i input capacitance - 3.7 5 pf
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 32 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 13. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. table 17. dynamic characteristics symbol parameter conditions standard-mod e i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - m s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - m s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - m s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - m s t hd;dat data hold time 0 - 0 - 0 - ns t vd;ack data valid acknowledge time [1] 0.3 3.45 0.1 0.9 0.05 0.45 m s t vd;dat data valid time [2] 0.3 3.45 0.1 0.9 0.05 0.45 m s t su;dat data set-up time 250 - 100 - 50 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - m s t high high period of the scl clock 4.0 - 0.6 - 0.26 - m s t f fall time of both sda and scl signals [3] [4] - 300 20 + 0.1c b [5] 300 - 120 ns t r rise time of both sda and scl signals - 1000 20 + 0.1c b [5] 300 - 120 ns t sp pulse width of spikes that must be suppressed by the input ?lter [6] - 50 - 50 - 50 ns output propagation delay t plh low to high propagation delay oe to ledn; mode2[1:0] = 01 - - - - - 150 ns t phl high to low propagation delay oe to ledn; mode2[1:0] = 01 - - - - - 150 ns output port timing t d(scl-q) delay time from scl to data output scl to ledn; mode2[3] = 1; outputs change on ack - - - - - 450 ns t d(sda-q) delay time from sda to data output sda to ledn; mode2[3] = 0; outputs change on stop condition - - - - - 450 ns
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 33 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the unde?ned region of scls falling edge. [4] the maximum t f for the sda and scl bus lines is speci?ed at 300 ns. the maximum fall time (t f ) for the sda output stage is speci?ed at 250 ns. this allows series protection resistors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum speci?ed t f . [5] c b = total capacitance of one bus line in pf. [6] input ?lters on the sda and scl inputs suppress noise spikes less than 50 ns. fig 18. de?nition of timing t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 19. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab285 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 1 (d1) bit 0 (d0) 1 / f scl t r t vd;dat acknowledge (a) stop condition (p)
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 34 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 14. test information r l = load resistor for ledn. r l for sda and scl > 1 k w (3 ma or less current). c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 20. test circuitry for switching times pulse generator v o c l 50 pf r l 500 w 002aab284 r t v i v dd dut v dd open gnd
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 35 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 15. package outline fig 21. package outline sot313-2 (lqfp48) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 q a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 36 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver fig 22. package outline sot778-4 (hvqfn48) terminal 1 index area terminal 1 index area references outline version european projection issue date iec jedec jeita sot778-4 - - - - - - - - - sot778-4 04-07-30 04-10-07 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included dimensions (mm are the original dimensions) hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 6 x 6 x 0.85 mm detail x e h d h l a c a 1 b d e b c a 12 13 24 48 37 1 25 36 e 2 e 1 e e 1/2 e 1/2 e a c b v m c w m y c y 1 x 0 2.5 5 mm scale unit mm 0.05 0.00 0.25 0.15 6.1 5.9 6.1 5.9 4.75 4.45 0.5 0.3 a 1 b 1 a (1) max d (1) e (1) e h 4.75 4.45 d h ee 1 l v 0.1 4.4 e 2 4.4 0.4 c 0.2 w 0.05 y 0.05 y 1 0.1
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 37 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 16. handling information all input and output pins are protected against electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 surface mount re?ow soldering description . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electrical circuits. the soldered joint provides both the mechanical and the electrical connection. there is no single soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for ?ne pitch smds. re?ow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and re?ow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. the re?ow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature pro?le. leaded packages, packages with solder balls, and leadless packages are all re?ow solderable. key characteristics in both wave and re?ow soldering are: ? board speci?cations, including the board ?nish, solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivity level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 38 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver ? process issues, such as application of adhesive and ?ux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath speci?cations, including temperature and impurities 17.4 re?ow soldering key characteristics in re?ow soldering are: ? lead-free versus snpb soldering; note that a lead-free re?ow process usually leads to higher minimum peak temperatures (see figure 23 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? re?ow temperature pro?le; this pro?le includes preheat, re?ow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classi?ed in accordance with t ab le 18 and 19 moisture sensitivity precautions, as indicated on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during re?ow soldering, see figure 23 . table 18. snpb eutectic process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 3 350 < 2.5 235 220 3 2.5 220 220 table 19. lead-free process (from j-std-020c) package thickness (mm) package re?ow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 39 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver for further information on temperature pro?les, refer to application note an10365 surface mount re?ow soldering description . 18. abbreviations msl: moisture sensitivity level fig 23. temperature pro?les for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 20. abbreviations acronym description ack acknowledge cdm charged device model dut device under test esd electrostatic discharge fet field-effect transistor hbm human body model i 2 c-bus inter-integrated circuit bus led light emitting diode lsb least signi?cant bit mm machine model msb most signi?cant bit pcb printed-circuit board pwm pulse width modulation rgb red/green/blue rgba red/green/blue/amber smbus system management bus
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 40 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 19. revision history table 21. revision history document id release date data sheet status change notice supersedes PCA9626_1 20090602 product data sheet - -
PCA9626_1 ? nxp b.v. 2009. all rights reserved. product data sheet rev. 01 2 june 2009 41 of 42 nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver 20. legal information 20.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 20.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 20.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. export control this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. 20.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. i 2 c-bus logo is a trademark of nxp b.v. 21. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors PCA9626 24-bit fm+ i 2 c-bus 100 ma 40 v led driver ? nxp b.v. 2009. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 2 june 2009 document identifier: PCA9626_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 22. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 device addresses . . . . . . . . . . . . . . . . . . . . . . . 7 7.1.1 regular i 2 c-bus slave address . . . . . . . . . . . . . 7 7.1.2 led all call i 2 c-bus address . . . . . . . . . . . . . . 8 7.1.3 led sub call i 2 c-bus addresses . . . . . . . . . . . 8 7.1.4 software reset i 2 c-bus address . . . . . . . . . . . 8 7.2 control register . . . . . . . . . . . . . . . . . . . . . . . . . 9 7.3 register de?nitions . . . . . . . . . . . . . . . . . . . . . 10 7.3.1 mode register 1, mode1 . . . . . . . . . . . . . . . . 12 7.3.2 mode register 2, mode2 . . . . . . . . . . . . . . . . 12 7.3.3 pwm0 to pwm23, individual brightness control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.3.4 grppwm, group duty cycle control . . . . . . . . 14 7.3.5 grpfreq, group frequency . . . . . . . . . . . . . 14 7.3.6 chase control . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3.7 ledout0 to ledout5, led driver output state . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.3.8 subadr1 to subadr3, i 2 c-bus subaddress 1 to 3 . . . . . . . . . . . . . . . . . . . . . . 21 7.3.9 allcalladr, led all call i 2 c-bus address. 21 7.4 active low output enable input . . . . . . . . . . . 22 7.5 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 22 7.6 software reset. . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7 individual brightness control with group dimming/blinking . . . . . . . . . . . . . . . . . . . . . . . 23 8 characteristics of the i 2 c-bus. . . . . . . . . . . . . 24 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1.1 start and stop conditions . . . . . . . . . . . . . 24 8.2 system con?guration . . . . . . . . . . . . . . . . . . . 24 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 25 9 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 26 10 application design-in information . . . . . . . . . 29 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 30 12 static characteristics. . . . . . . . . . . . . . . . . . . . 31 13 dynamic characteristics . . . . . . . . . . . . . . . . . 32 14 test information . . . . . . . . . . . . . . . . . . . . . . . . 34 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 35 16 handling information . . . . . . . . . . . . . . . . . . . 37 17 soldering of smd packages . . . . . . . . . . . . . . 37 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 37 17.2 wave and re?ow soldering . . . . . . . . . . . . . . . 37 17.3 wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 37 17.4 re?ow soldering. . . . . . . . . . . . . . . . . . . . . . . 38 18 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 19 revision history . . . . . . . . . . . . . . . . . . . . . . . 40 20 legal information . . . . . . . . . . . . . . . . . . . . . . 41 20.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 20.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.3 disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 41 20.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21 contact information . . . . . . . . . . . . . . . . . . . . 41 22 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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